Развитие ассоциативных параллельных архитектур

Развитие ассоциативных параллельных архитектур

Автор: Снытникова Татьяна Валентиновна

Журнал: Проблемы информатики @problem-info

Рубрика: Параллельное системное программирование и вычислительные технологии

Статья в выпуске: 2 (43), 2019 года.

Бесплатный доступ

Существующие в настоящее время аппаратные средства преимущественно ориентированы на адресную обработку данных. В работе представлен обзор ассоциативных параллельных архитектур от первого промышленного ассоциативного процессора STARAN до современного ATLAS Fast TracKcr. Каждая из рассматриваемых архитектур была построена иод решение конкретных задач, которые не могли быть эффективно решены на системах другой архитектуры

Ассоциативные параллельные архитектуры

Короткий адрес: https://sciup.org/143170652

IDR: 143170652

Список литературы Развитие ассоциативных параллельных архитектур

  • Krikelis A., Weems С. С. Associative processing and processors // Computer. 1994. 27(11). P. 12 17.
  • Pagiamtzis K., Sheikholeslami A. Content-addressable memory (cam) circuits and architectures: a tutorial and survey // IEEE Journal of Solid-State Circuits. 2006. 41(3). P. 712-727.
  • Kocak T., Basci F. A power-efficient team architecture for network forwarding tables // Journal of Systems Architecture. 2006. 52(5). P. 307 - 314.
  • Noda H., Inoue K., Kuroiwa M. and el. A cost-efficient high-performance dynamic team with pipelined hierarchical searching and shift redundancy architecture // IEEE Journal of Solid-State Circuits. 2005. 40: P. 245-253.
  • Potter J. L. Associative Computing: A Programming Paradigm for Massively Parallel Computers / Perseus Publishing. 1991.
  • Jalaleddine S. M. Associative memories and processors: The exact match paradigm // Journal of King Saud University - Computer and Information Sciences. 1999. ll(Supplement С). P. 45-67.
  • GOST 15971-90. Sistemv obrabotki informatsii. Terminv i opredeleniva (Information processing systems. Terms and Definitions]. 1991. P. 4.
  • Clements A. The Principles of Computer Hardware / Oxford University Press, 2000.
  • Tanenbaum A. S. Structured Computer Organization / Prentice Hall PTR, 1998.
  • Rudolph J. A. A production implementation of an associative array processor: Staran. In Proceedings of the December 5-7, 1972, Fall Joint Computer Conference, Part I, AFIPS '72 (Fall, part I), New York, NY, USA, 1972. ACM. P. 229-241.
  • Foster С. C. Content addressable parallel processors / Caxton C. Foster / Van Nostrand Reinhold New York, 1976.
  • Batcher К. E. Design of a massively parallel processor // IEEE Transactions on Computers. 1980. 29(9). P. 836-840.
  • Batcher К. E. Staran parallel processor system hardware //In Proceedings of the May 6-10, 1974, National Computer Conference and Exposition, AFIPS '74. New York, NY, USA, 1974. ACM. P. 405-410.
  • GER-15637A. STARAN S APPLE Programming Manual / GOODYEAR AEROSPACE CORPORATION, OHIO. 1973.
  • Davis E. W. Staran parallel processor system software // Proceedings of the May 6-10, 1974, National Computer Conference and Exposition, AFIPS '74, New York, NY, USA, 1974. ACM. P. 17-22.
  • Batcher К. E. Bit-serial parallel processing systems // IEEE Transactions on Computers. 1982. 31(5). P 377-384.
  • Uhr L. M. Algorithm-Structured Computer Arrays and Networks: Architectures and Processes for Images, Precepts, Models, Information / Academic Press, Inc., Orlando, FL, USA, 1984.
  • Wang H., Walker R. A. Implementing a scalable asc processor / Parallel and Distributed Processing Symposium, 2003. Proceedings. International. 2003.
  • Mingxian J. Associative operations from masc to GPU // PDPTA'15 - The 21st International Conference on Parallel and Distributed Processing Techniques and Applications. Las Vegas: CSREA Press, 2015. P. 388-393.
  • Snvtnikova T. V., Snvtnikov A. V. Implementation of the star-machine on GPU // NCC Bulletin. 2016. 39. P. 51-60. '
  • Снытникова T. В., Непомнящая A. HI. Решение задач на графах с помощью STAR- машины, реализуемой на графических ускорителях // Прикладная дискретная математика. 2016. № 3(33). С. 98-115. Т. В. Снытникова
  • Higuchi Т., Kitano Н., Furuva Т., Handa К., Kokubu A., Takahashi N. Ixm2: A parallel associative processor for knowledge processing // Editors: Thomas L. Dean and Kathleen McKeown, AAAI. AAAI Press / The MIT Press. 1991. P. 296-303.
  • Higuchi T., Furuva T., Handa K., Takahashi N., Nishivama H., Kokubu A. Ixm2: A parallel associative processor //In Proceedings of the 18th Annual International Symposium on Computer Architecture, ISCA '91, New York, NY, USA, 1991. ACM. P. 22-31.
  • Higuchi T., Furuva T., Handa K., Kokubu A. Initial evaluation of a parallel associative processor IXM2 // Microprocessing and Microprogramming. 1991. 31(1). P. 89 - 92.
  • Kitano H. Chapter ASTRAL: An Implementation on the IXM2 Associative Memory Processor / Speech-to-Speech Translation: A Massively Parallel Memory-Based Approach. Springer US, Boston, MA, 1994. P. 135-155.
  • Kitano H., Higuchi T., Tomita M. Massively parallel spoken language processing using a parallel associative processor IXM2 // The First International Conference on Spoken Language Processing, ICSLP 1990, Kobe, Japan. 1990. P. 917-920.
  • Oi K., Sumita E., Furuse O., Iida H., Higuchi T. Real-time spoken language translation using associative processors // Proceedings of the Fourth Conference on Applied Natural Language Processing. Stroudsburg, PA, USA, 1994., ANLC'94. P. 101-106.
  • Smith D. E., Hall J. S., Miyake K. Rutger's CAM2000 Chip Architecture / Rutgers University, Department of Computer Science, Laboratory for Computer Science Research, 1993.
  • Smith D. E., Hall J. S., Miyake K. Rutger's cam2000 chip architecture. Technical report, 1993.
  • Hsu С. H., Smith D. E., Levy S. Linear-C: A data-parallel extension to C / Technical Report LCSR-TR-273, Computer Science Department, Rutgers University, 1996.
  • Volpi G. Associative memory computing power and its simulation / Technical Report ATL- DAQ-PROC-2014-018, CERN, Geneva.2014.
  • Annovi A., Beretta M., Bossini E., Crescioli F., Dell'Orso M., Giannetti P., Piendibene M., Sacco I., Sartori L., Tripiccione R. Associative memory design for the fasttrack processor (FTK) at ATLAS. // Real Time Conference (RT). 2010. 17th IEEE-NPSS. P. 1-3.
  • The ATLAS Collaboration. The atlas experiment at the CERN Large Hadron Collider // Journal of Instrumentation. 2008. 3(08). P. S08003.
  • The ATLAS Collaboration. Expected performance of the ATLAS experiment: detector, trigger and physics. CERN, Geneva, 2009.
  • Cho A. The discovery of the higgs boson // Science. 2012. 338(6114). P 1524-1525.
  • Maznas I. Ftk: The hardware fast tracker of the atlas experiment at CERN // EPJ Web Conf. 2017. 137. P. 12001.
  • Biesuz N., Citraro S., Donati S., et al. Highly parallelized pattern matching execution for atlas event real time reconstruction // IEEE Transactions on Nuclear Science (TNS). 2016. 63. P. 1147-1154.
  • Pagiamtzis K., Sheikholeslami A. Content-addressable memory (CAM) circuits and architectures: A tutorial and survey. IEEE Journal of Solid-State Circuits. 2006. 41(3). P. 712-727.
  • Dell'Orso M., Ristori L. VLSI structures track finding // Nucl. Instr. and Meth. A. 1989. 278. P. 436-440.
  • Wissing Ch., Baird A., Baldinger R., et al. Performance of the HI Fast Track trigger: Operation and commissioning results // Proceedings of the 14th IEEE-NPSS Conference on Real Time, RTC'05, Washington, DC, USA, 2005. IEEE Computer Society, P. 233-236.
  • Bardi A., et al. The CDF online silicon vertex tracker // Nucl. Instrum. Meth. 2002. A485. P. 178-182.
  • Annovi A., Bardi A., Bitossi M., et al. A VLSI processor for fast track finding based on content addressable memories // IEEE Transactions on Nuclear Science. 2006. 53(4). P 2428-2433.
  • Masi S. Periodic report summary 1 - FTK (Fast Tracker for Hadron Collider experiments) // Technical Report 324318, Industry-Academia Partnerships and Pathways, Italy. 2015.
  • Asbah N. A hardware fast tracker for the ATLAS trigger // Physics of Particles and Nuclei Letters. 2016. 13(5). P. 527-531.
  • Maznas I. FTK: The hardware Fast TracKer of the ATLAS experiment at CERN // Technical Report ATL-DAQ-PROC-2016-033, CERN, Geneva, 2016.
  • Sotiropoulou C. L., Gkaitatzis S., Annovi A., et al. A Multi-Core FPGA-Based 2D-Clustering Implementation for Real-Time Image Processing // IEEE Trans. Nucl. Sci. 2014. 61(6). P. 3599-3606.
  • Okumura Y., Liu T., Olsen J., et al. Atca-based atlas FTK input interface system // Journal of Instrumentation. 2015. 10(04). P. C04032.
  • Ng K.F., and Rochester Institute of Technology. Computer Engineering / Novel Low Power CAM Architecture. Rochester Institute of Technology, 2008.
  • Xu W., Zhang T., Chen Y. Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010. 18(1). P. 66-74.
  • Imani M., Rahimi A., Rosing T. S. Resistive configurable associative memory for approximate computing / 2016 Design, Automation Test in Europe Conference Exhibition (DATE).2016. P. 13271332.
  • Стемпковский A. JL, Климов А. В., Левченко H. H., Окунев А. С. Методы адаптации параллельной потоковой вычислительной системы под задачи отдельных классов // Информационные Технологии И Вычислительные Системы. 2009. № 3. С. 12-21.
  • Змеев Д. Н. Средства проектирования высокопроизводительных потоковых вычислительных систем // Проблемы Разработки Перспективных Микро- И Наноэлектронных Систем (МЭС). 2016. № 2. С. 159-163.
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