Организация полностью самопроверяемой схемы встроенного контроля на основе метода логического дополнения до равновесного кода "2 из 4"
Автор: Ефанов Д.В., Сапожников В.В., Сапожников вЛ.В., Пивоваров Д.В.
Журнал: Труды Института системного программирования РАН @trudy-isp-ran
Статья в выпуске: 2 т.30, 2018 года.
Бесплатный доступ
Рассматривается задача синтеза самопроверяемой схемы встроенного контроля с оптимизацией структурной избыточности на основе использования метода логического дополнения до равновновесного кода «2 из 4». Разработан способ доопределения значений контрольных функций, позволяющий пошагово устанавливать их вид и при этом обеспечивать решение задачи тестирования соответствующих элементов сложения по модулю два и схемы тестера. При этом в значения функций вводятся неопределенности, что позволяет минимизировать сами функции, и соответственно, упрощать схему блока контрольной логики.
Схема встроенного контроля, логическое дополнение, равновесный код, код
Короткий адрес: https://sciup.org/14916576
IDR: 14916576 | DOI: 10.15514/ISPRAS-2018-30(2)-6
Список литературы Организация полностью самопроверяемой схемы встроенного контроля на основе метода логического дополнения до равновесного кода "2 из 4"
- Kubalík P., Kubátová H. Parity Codes Used for On-Line Testing in FPGA. Acta Polytechnika, 2005, Vol. 45, No. 6, pp. 53-59.
- Ubar R., Raik J., Vierhaus H.-T. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source). -Information Science Reference, Hershey -New York, IGI Global, 2011, 578 p.
- Borecký J., Kohlík M., Kubátová H. Parity Driven Reconfigurable Duplex System. Microprocessors and Microsystems, 2017, Vol. 52, pp. 251-260, DOI: 10.1016/j.micpro.2017.06.015
- Objects and Methods of On-Line Testing for Safe Instrumentation and Control Systems/A.V. Drozd, V.S. Kharchenko, S.G. Antoshchuk, Ju.V. Drozd, M.A. Drozd, Yu.Yu. Sulima. Kharkov, National Aerospace University "KhAI", 2012, 614 p..
- Parkhomenko P.P., Sogomonyan E.S. Technical Diagnosis Fundamentals (Diagnostic Algorithm Optimization, Apparatus Means). Moscow: Energoatomizdat, 1981, 320 p..
- Sogomonyan, E.S., Slabakov E.V. Self-Checking Devices and Fault-Tolerant Systems. Moscow: Radio & Communication, 1989, 208 p..
- Berger J.M. А Note on Error Detecting Codes for Asymmetric Channels. Information and Control, 1961, vol. 4, issue 1, pp. 68-73, DOI: 10.1016/S0019-9958(61)80037-5
- Freiman C.V. Optimal Error Detection Codes for Completely Asymmetric Binary Channels. Information and Control, 1962, Vol. 5, Issue 1, pp. 64-71, DOI: 10.1016/S0019-9958(62)90223-1
- Efanov D.V., Sapozhnikov V.V., Sapozhnikov Vl.V. Conditions for Detecting a Logical Element Fault in a Combination Device under Concurrent Checking Based on Berger`s Code. Automation and Remote Control, 2017, Vol. 78, Issue 5, pp. 891-901, DOI: 10.1134/S0005117917050113
- Sogomonyan E.S., Gössel M. Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs. Journal of Electronic Testing: Theory and Applications, 1993, Vol. 4, Issue 4, pp. 267-281, DOI: 10.1007/BF00971975
- Busaba F.Y., Lala P.K. Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors. Journal of Electronic Testing: Theory and Applications, 1994, Vol. 5, Issue 1, pp. 19-28, DOI: 10.1007/BF00971960
- Matrosova A.Yu., Levin I., Ostanin S.A. Self-Checking Synchronous FSM Network Design with Low Overhead. VLSI Design, 2000, Vol. 11, Issue 1, pp. 47-58, DOI: 10.1155/2000/46578
- Ostanin S. Self-Checking Synchronous FSM Network Design for Path Delay Faults. Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29 -October 2, 2017, pp. 696-699, DOI: 10.1109/EWDTS.2017.8110129
- Nicolaidis M., Zorian Y. On-Line Testing for VLSI -А Compendium of Approaches. Journal of Electronic Testing: Theory and Applications, 1998, Issue 12, pp. 7-20, DOI: 10.1023/A:1008244815697
- Piestrak S.J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes. -Wrocław: Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995, 111 p.
- Sapozhnikov V.V., Sapozhnikov Vl.V., Dmitriev A.V., Morozov A.V., Göessel M. Organization of Functional Checking of Combinational Circuits by the Logic Complement Method, Yelektronnoje modelirovanije , 2002, Vol. 24, Issue 6, pp. 51-66..
- Goessel M., Morozov A.V., Sapozhnikov V.V., Sapozhnikov Vl.V. Logic Complement, a New Method of Checking the Combinational Circuits. Automation and Remote Control, 2003, Vol. 64, Issue 1, pp. 153-161, DOI: 10.1023/A:1021884727370
- Saposhnikov Vl.V., Dmitriev A., Goessel M., Saposhnikov V.V. Self-Dual Parity Checking -a New Method for on Line Testing. Proceedings of 14th IEEE VLSI Test Symposium, 28 April -1 May 1996, Princeton, NJ, USA, pp. 162-168, DOI: 10.1109/VTEST.1996.510852
- Dmitriev A., Saposhnikov V., Saposhnikov Vl., Goessel M., Moshanin V., Morosov A. New Self-Dual Circuits for Error Detection and Testing. VLSI Design, 2000, Vol. 11, Issue 1, pp. 1-21, DOI: 10.1155/2000/84720
- Göessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking: Edition 1. -Dordrecht: Springer Science+Business Media B.V., 2008, 184 p.
- Sen S.K. A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don’t Cares. National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology, Sikkim, held during 22-24 December, 2010.
- Das D.K., Roy S.S., Dmitiriev A., Morozov A., Gössel M. Constraint Don’t Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes. Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33-40.
- Sapozhnikov V.V., Sapozhnikov Vl.V., Efanov D.V. Design of Self-Checking Concurrent Error Detection Systems Based on "2-out-of-4" Constant-Weight Code. Problemy upravlenija , 2017, Issue 1, Pp. 57-64..
- Sapozhnikov V.V., Sapozhnikov Vl.V. Self-Checking Discrete Devices. St. Petersburg: Energoatomizdat, 1992, 224 p..
- Sapozhnikov V., Sapozhnikov Vl., Efanov D. Concurrent Error Detection of Combinational Circuits by the Method of Boolean Complement on the Base of «2-out-of-4» Code. Proceedings of 14th IEEE East-West Design & Test Symposium (EWDTS`2016), Yerevan, Armenia, October 14-17, 2016, pp. 126-133, DOI: 10.1109/EWDTS.2016.7807677
- Pivovarov D.V. Formation of concurrent error detection systems in multiple-output combinational circuits using the Boolean complement method based on constant-weight codes. Avtomatika na transporte , 2018, Vol. 4, Issue 1, pp. 130-148..
- Sapozhnikov V.V., Sapozhnikov Vl.V., Efanov D.V., Pivovarov D.V. Synthesis of concurrent error detection systems of multioutput combinational circuits based on Boolean complement method. Vestnik Tomskogo gosudarstvennogo universiteta: Upravlenije, vychislitel`naya technika I informatika , 2017, Issue 4, pp. 69-80, DOI: 10.17223/19988605/41/9
- Aksjonova G.P. Necessary and Sufficient Conditions for Design of Completely Checkable Modulo 2 Convolution Circuits. Automation and Remote Control, 1979, Vol. 40, Issue 9, pp. 1362-1369.
Статья научная
