A Two Layers Novel Low-Cost and Optimized Embedded Board Based on TMS320C6713 DSP and Spartan-3 FPGA

Автор: Bahram Rashidi, Ghader Karimian

Журнал: International Journal of Modern Education and Computer Science (IJMECS) @ijmecs

Статья в выпуске: 4 vol.5, 2013 года.

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This paper presents the design and implementation of a new low-cost and minimum embedded board based on TMS320C6713 (PYP 208-PIN (PQFP)) DSP and Spartan-3 (XCS400-4PQG208C) FPGA in two layers with mount elements on two sides of the board. The proposed embedded board was developed satisfactorily for different applications such as data acquisition of sensor’s with serial port, control units, finite state machines, signal processing algorithms, navigation computing, Kalman filtering etc. Goal of the design was to implement as many as possible low-cost and minimum sizes of the board, also to receive input signals in a short time period and as real time. The board features are include: mount elements in two side of the board for minimization of the proposed board and also placed decoupling capacitors (by pass) for the DSP and FPGA in bottom layer of board strictly below these two ICs because should be placed as close as possible to the power supply pins DSP and FPGA, GND polygon layer is used in total top layer and microcomputer ground for DSP & FPGA in bottom layer, use FPGA for two aim ones for implementation of glue logic total of board and interface between serial connectors, use three RS-232 serial port, one RS-422, and SPI serial port on FPGA, use MT48LC16M16A SDRAM-256MB(4*4MB*16), Am29LV400B Flash memory 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) and XCF02S configuration PROM. The size of the proposed embedded board is 11.1cm*17. 7cm so this board is optimized of aspect cost, performance, power, weight, and size.

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Embedded system design, embedded processors, reconfigurable architectures, Low-Cost, Digital Algorithms, microcomputer ground, data acquisition, real time

Короткий адрес: https://sciup.org/15014542

IDR: 15014542

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