Structural and architectural organization of IP-blocks for dynamically reconfigurable networks-on-chip

Dynamic reconfiguration of Network-on-chip (NOC) allows to essentially expand its functionality (and thereby application area) and can be used for fault mitigation. In this paper, we consider dynamic reconfiguration process of NOC produced as ASIC, requirements and constraints that should be taken into account by IP-blocks designers. We suggest an approach of IP-blocks development for NOC’s with different granularity of reconfiguration modules. We suggest the rules allow to exclude faults (such as loss of data, incorrect transmission and processing of data) during configuration process.