Methods of creation the nanodimentional VLSI and «systems on crystal» (SoC) with lower static power

For nanodimentional CMOS technologies (90 nanometers and more low) the major power consumed by schemes at the expense of leakage static currents, is the basic problem for developers. According to the international road map for semiconductor branch (ITRS) with reduction of the technological sizes static power of CMOS starts to dominate over other components of power consumption. In paper methods of decrease in power consumption of CMOS devices in an expectation mode at a stage of scheme-technical designing are considered. The given methods allow to reduce considerably the currents of leakage caus-ing magnifications of power consumption in up-to-date CMOS.